URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_wbmux.v] - Rev 373

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5188d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5190d 06h	/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5190d 15h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wbmux.v
350	Adding new OR1200 processor to ORPSoCv2	julius	5193d 10h	/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_wbmux.v