URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Rev 362

Rev	Log message	Author	Age	Path
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5197d 01h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5200d 01h	/orpsoc_top.v
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5440d 06h	/orpsoc_top.v
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5497d 22h	/orpsoc_top.v
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5508d 05h	/orpsoc_top.v
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5611d 09h	/orpsoc_top.v
6	Checking in ORPSoCv2	julius	5673d 21h	/orpsoc_top.v