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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Rev 478

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439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5081d 13h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 5109d 14h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 5116d 09h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5166d 21h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5168d 11h /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5171d 11h /orpsoc_top.v
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5411d 16h /orpsoc_top.v
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5469d 08h /orpsoc_top.v
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5479d 15h /orpsoc_top.v
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5582d 19h /orpsoc_top.v
6 Checking in ORPSoCv2 julius 5645d 07h /orpsoc_top.v

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