OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Rev 534

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
506	ORPSoC or1200 interrupt and syscall generation test	julius	5019d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5074d 13h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5134d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5162d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5169d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5219d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5221d 04h	/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5224d 04h	/orpsoc_top.v
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5464d 10h	/orpsoc_top.v
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5522d 02h	/orpsoc_top.v
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5532d 09h	/orpsoc_top.v
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5635d 12h	/orpsoc_top.v
6	Checking in ORPSoCv2	julius	5698d 01h	/orpsoc_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.