URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ram_wb/] [ram_wb_b3.v] - Rev 518

Rev	Log message	Author	Age	Path
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	5075d 23h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5107d 14h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
412	ORPSoC update - Rearranged Xilinx ML501, simulations working again.	julius	5139d 05h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5194d 12h	/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_sc_sw.v
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5538d 16h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v
6	Checking in ORPSoCv2	julius	5671d 08h	/openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v