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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [uart_receiver.v] - Rev 363

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363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.
julius 5188d 04h /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5189d 18h /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v
6 Checking in ORPSoCv2 julius 5666d 15h /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_receiver.v

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