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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [uart_transmitter.v] - Rev 862

Rev	Log message	Author	Age	Path
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5220d 17h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v
360	First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken	julius	5222d 07h	/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v
6	Checking in ORPSoCv2	julius	5699d 03h	/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_transmitter.v