| Rev |
Log message |
Author |
Age |
Path |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4967d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
5012d 20h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
5013d 23h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
5014d 17h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5048d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5069d 02h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5069d 05h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5074d 06h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5100d 20h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5114d 15h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
5120d 22h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5127d 15h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5142d 19h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5145d 01h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
5148d 00h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5193d 07h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5194d 16h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5194d 21h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5195d 15h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5196d 21h |
/openrisc/trunk/orpsocv2/sim/bin/Makefile |
