URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [definesgen.inc] - Rev 495

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5165d 03h	/openrisc/trunk/orpsocv2/sim/bin/definesgen.inc
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5167d 20h	/openrisc/trunk/orpsocv2/sim/bin/definesgen.inc