OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [refdesign-or1ksim.cfg] - Rev 620

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 5055d 13h /openrisc/trunk/orpsocv2/sim/bin/refdesign-or1ksim.cfg
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 5107d 07h /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 5114d 00h /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5183d 05h /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5466d 07h /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg
6 Checking in ORPSoCv2 julius 5658d 02h /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.