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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [apps/] [dhry/] [dhry.c] - Rev 393

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393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5013d 12h /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.c
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5061d 03h /openrisc/trunk/orpsocv2/sw/dhry/dhry.c
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5062d 09h /openrisc/trunk/orpsocv2/sw/dhry/dhry.c
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5345d 10h /openrisc/trunk/orpsocv2/sw/dhry/dhry.c
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5423d 06h /openrisc/trunk/orpsocv2/sw/dhry/dhry.c
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5474d 17h /openrisc/trunk/orpsocv2/sw/dhry/dhry.c
6 Checking in ORPSoCv2 julius 5537d 05h /openrisc/trunk/orpsocv2/sw/dhry/dhry.c

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