URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [board/] [include/] [board.h] - Rev 701

Rev	Log message	Author	Age	Path
506	ORPSoC or1200 interrupt and syscall generation test	julius	4968d 13h	/openrisc/trunk/orpsocv2/sw/board/include/board.h
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5023d 19h	/openrisc/trunk/orpsocv2/sw/board/include/board.h
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5118d 09h	/openrisc/trunk/orpsocv2/sw/board/include/board.h
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5123d 14h	/openrisc/trunk/orpsocv2/sw/board/include/board.h
373	ORPSoCv2 software update for compatibility with OR toolchain 1.0	julius	5156d 13h	/board.h
361	OPRSoCv2 - adding things left out in last check-in	julius	5170d 10h	/board.h
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5172d 11h	/board.h
349	ORPSoCv2 update with new software and makefile update	julius	5173d 15h	/board.h