URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [board/] [include/] [board.h] - Rev 393

Rev	Log message	Author	Age	Path
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5143d 04h	/openrisc/trunk/orpsocv2/sw/board/include/board.h
373	ORPSoCv2 software update for compatibility with OR toolchain 1.0	julius	5176d 04h	/board.h
361	OPRSoCv2 - adding things left out in last check-in	julius	5190d 01h	/board.h
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5192d 01h	/board.h
349	ORPSoCv2 update with new software and makefile update	julius	5193d 05h	/board.h