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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] [Makefile] - Rev 495

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Rev Log message Author Age Path
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5010d 18h /openrisc/trunk/orpsocv2/sw/bootrom/Makefile
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5092d 10h /openrisc/trunk/orpsocv2/sw/bootrom/Makefile
361 OPRSoCv2 - adding things left out in last check-in julius 5139d 06h /openrisc/trunk/orpsocv2/sw/bootrom/Makefile

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