OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] [Makefile] - Rev 812

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5039d 17h /openrisc/trunk/orpsocv2/sw/bootrom/Makefile
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5121d 08h /openrisc/trunk/orpsocv2/sw/bootrom/Makefile
361 OPRSoCv2 - adding things left out in last check-in julius 5168d 05h /openrisc/trunk/orpsocv2/sw/bootrom/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.