URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] [bootrom.S] - Rev 441

Rev	Log message	Author	Age	Path
415	ORPSoC - ML501 update, working again. Documentation update including information on ML501 build OR1200 updates to do with instruction cache tag signal when invalidate instruction used. Added ability to define address to pass to SPI flash when booting. Added SPI sw test for board which allows inspection of data in a flash.	julius	5111d 01h	/openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	5117d 20h	/openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S
361	OPRSoCv2 - adding things left out in last check-in	julius	5169d 22h	/openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S