URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Rev 475

Rev	Log message	Author	Age	Path
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	5064d 14h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
470	ORPSoC OR1200 crt0 updates.	julius	5068d 14h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5123d 00h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5143d 09h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
373	ORPSoCv2 software update for compatibility with OR toolchain 1.0	julius	5176d 09h	/crt0.S
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5192d 06h	/crt0.S
349	ORPSoCv2 update with new software and makefile update	julius	5193d 10h	/crt0.S