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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Rev 483

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Rev Log message Author Age Path
483 ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build. julius 5039d 20h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 5049d 10h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
470 ORPSoC OR1200 crt0 updates. julius 5053d 10h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 5107d 20h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5128d 06h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5161d 05h /crt0.S
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5177d 02h /crt0.S
349 ORPSoCv2 update with new software and makefile update julius 5178d 06h /crt0.S

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