URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Rev 418

Rev	Log message	Author	Age	Path
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5126d 23h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
373	ORPSoCv2 software update for compatibility with OR toolchain 1.0	julius	5159d 22h	/crt0.S
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5175d 19h	/crt0.S
349	ORPSoCv2 update with new software and makefile update	julius	5176d 23h	/crt0.S