URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Rev 442

Rev	Log message	Author	Age	Path
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5105d 15h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5126d 00h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
373	ORPSoCv2 software update for compatibility with OR toolchain 1.0	julius	5159d 00h	/crt0.S
354	Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer interrupt to increment variable now in place instead of calling customisable interrupt vector handler Changed all system frequencies in design to 50MHz.	julius	5174d 21h	/crt0.S
349	ORPSoCv2 update with new software and makefile update	julius	5176d 01h	/crt0.S