URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [exceptions.c] - Rev 418

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5119d 00h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5126d 23h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c
349	ORPSoCv2 update with new software and makefile update	julius	5176d 23h	/exceptions.c