URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [link.ld] - Rev 442

Rev	Log message	Author	Age	Path
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5086d 00h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5126d 01h	/openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld
349	ORPSoCv2 update with new software and makefile update	julius	5176d 01h	/link.ld