URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [ethmac/] [sim/] [ethmac-rxtx.c] - Rev 438

Rev	Log message	Author	Age	Path
411	Improved ethmac testbench and software. Renamed some OR1200 library functions to be more generic. Fixed bug with versatile_mem_ctrl for Actel board. Added ability to simulate gatelevel modules alongside RTL modules in board build.	julius	5166d 18h	/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c
409	ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it. Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build. Updated documentation.	julius	5167d 18h	/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c
395	ORPSoCv2 moving ethernet tests to correct place	julius	5174d 16h	/openrisc/trunk/orpsocv2/sw/tests/eth/sim/eth-rxtx.c
349	ORPSoCv2 update with new software and makefile update	julius	5224d 17h	/eth-rxtx.c