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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-dctest.c] - Rev 803

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Rev	Log message	Author	Age	Path
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	5033d 22h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5093d 16h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5113d 07h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5133d 17h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
349	ORPSoCv2 update with new software and makefile update	julius	5183d 18h	/or1200-dctest.c

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