URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-mmu.c] - Rev 439

Rev	Log message	Author	Age	Path
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5102d 21h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5122d 13h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5142d 22h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
373	ORPSoCv2 software update for compatibility with OR toolchain 1.0	julius	5175d 22h	/or1200-mmu.c
351	OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO	julius	5192d 19h	/or1200-mmu.c
349	ORPSoCv2 update with new software and makefile update	julius	5192d 23h	/or1200-mmu.c