URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ticksyscall.S] - Rev 820

Rev	Log message	Author	Age	Path
671	ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model	julius	4717d 23h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	5049d 15h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	5108d 21h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S
393	ORPSoCv2 software rearrangement in progress. Basic tests should now run again.	julius	5129d 07h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S
349	ORPSoCv2 update with new software and makefile update	julius	5179d 07h	/or1200-ticksyscall.S