URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [main.c] - Rev 800

Rev	Log message	Author	Age	Path
800	FreeRTOSV6.1.1 add or32_dma demo task for test dcache manuplation function add simple driver of wb_dma	filepang	4581d 12h	/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c
799	FreeRTOSV6.1.1 add cache related function from u-boot from OpenRISC enable I/D cache if present	filepang	4582d 13h	/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c
666	FreeRTOSV6.1.1 minimal set of standard demo task is working	filepang	4736d 00h	/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c
649	porting some of standard demo tasks fix serial port(UART) interrupt handler	filepang	4811d 00h	/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c
622	update uart driver for support multiple uart cores from http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/sw/drivers/uart	filepang	4851d 01h	/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c
621	update sim.cfg for newer version of Or1ksim. remove unused files. cleanup source code. insert non-local jump(setjmp) in xPortStartScheduler. now xPortStartScheduler() will be returned by xPortEndScheduler().	filepang	4852d 17h	/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c
584	Initial port of FreeRTOS by filepang (Kim Sung Su).	jeremybennett	4867d 03h	/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c