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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Rev 1772

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1765 root 5747d 12h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
1252 preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. lampret 7602d 09h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7852d 08h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7895d 11h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8124d 05h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
788 Some of the warnings fixed. lampret 8285d 20h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
636 Fixed combinational loops. lampret 8341d 15h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8346d 10h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
595 Fixed 'the NPC single-step fix'. lampret 8355d 21h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8360d 05h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8371d 03h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ctrl.v

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