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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_tlb.v] - Rev 1772

Rev	Log message	Author	Age	Path
1765		root	5747d 12h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v
1214	Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.	simons	7665d 23h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7852d 08h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	8083d 15h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8332d 06h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8346d 09h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8371d 02h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dmmu_tlb.v