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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5718d 12h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
1171	Added embedded memory QMEM.	lampret	7790d 19h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7823d 08h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7883d 10h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8257d 16h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
636	Fixed combinational loops.	lampret	8312d 15h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8322d 03h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8325d 21h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8330d 05h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8342d 03h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_dpram_32x32.v