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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Rev 1765

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1765 root 5747d 21h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1252 preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. lampret 7602d 18h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7852d 17h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1155 No functional change. Only added customization for exception vectors. lampret 7898d 22h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8127d 22h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8134d 18h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
993 Fixed IMMU bug. lampret 8140d 18h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
977 Added store buffer. lampret 8144d 00h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8178d 22h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8332d 16h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8346d 19h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8351d 12h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
595 Fixed 'the NPC single-step fix'. lampret 8356d 06h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8356d 12h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
571 Changed alignment exception EPCR. Not tested yet. lampret 8359d 23h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
570 Fixed order of syscall and range exceptions. lampret 8360d 01h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8360d 14h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8371d 12h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v

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