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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Rev 1772

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1765 root 5755d 02h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_mem2reg.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7859d 22h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_mem2reg.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8135d 03h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_mem2reg.v
788 Some of the warnings fixed. lampret 8293d 10h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_mem2reg.v
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8294d 06h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_mem2reg.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8367d 19h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_mem2reg.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8378d 17h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_mem2reg.v

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