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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_rfram_generic.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5747d 22h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_rfram_generic.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7852d 18h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_rfram_generic.v
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	8127d 22h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_rfram_generic.v
871	Generic flip-flop based memory macro for register file.	lampret	8215d 04h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_rfram_generic.v