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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x8.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5718d 12h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x8.v
1214	Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.	simons	7636d 23h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x8.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7823d 08h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x8.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7883d 10h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x8.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	8054d 15h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x8.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8342d 03h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_2048x8.v