URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Rev 1772

Rev	Log message	Author	Age	Path
1765		root	5755d 02h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7859d 22h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8186d 03h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8378d 17h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_xcv_ram32x8d.v