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[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1777

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1765 root 5742d 05h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1164 This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'. 7847d 01h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7890d 04h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1155 No functional change. Only added customization for exception vectors. lampret 7893d 06h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7906d 07h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7907d 03h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 8026d 19h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1078 Previous check-in was done by mistake. mohor 8067d 13h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1077 Signal scanb_sen renamed to scanb_en. mohor 8067d 13h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8078d 08h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1055 Removed obsolete comment. lampret 8110d 01h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8117d 22h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8118d 09h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8118d 23h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8122d 03h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8122d 06h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8135d 02h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
984 Disable SB until it is tested lampret 8138d 06h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
977 Added store buffer. lampret 8138d 08h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8141d 22h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_defines.v

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