OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_top.v] - Rev 1777

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5742d 05h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
1164 This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'. 7847d 01h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8078d 08h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
788 Some of the warnings fixed. lampret 8280d 13h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
668 Lapsus fixed. simons 8323d 13h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8327d 00h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8341d 03h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8354d 22h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8365d 20h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_dmmu_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.