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1765 root 5638d 03h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
1164 This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'. 7742d 22h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7877d 22h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
1038 Fixed a typo, reported by Taylor Su. lampret 8013d 06h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8069d 03h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
737 Added alternative for critical path in DU. lampret 8192d 01h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8222d 21h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8237d 00h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8246d 17h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8250d 19h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8261d 17h /or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_du.v

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