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[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5638d 02h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mem2reg.v
1164	This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'.		7742d 22h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mem2reg.v
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	8018d 03h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mem2reg.v
788	Some of the warnings fixed.	lampret	8176d 10h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mem2reg.v
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8177d 06h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mem2reg.v
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8250d 19h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mem2reg.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8261d 17h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_mem2reg.v