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[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Rev 1777

Rev	Log message	Author	Age	Path
1765		root	5742d 06h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
1164	This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'.		7847d 02h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8173d 06h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8365d 20h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_xcv_ram32x8d.v