URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [README] - Rev 1768

Rev	Log message	Author	Age	Path
1765		root	5769d 07h	/or1k/branches/stable_0_1_x/or1ksim/README
1356	This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'.		7257d 20h	/or1k/branches/stable_0_1_x/or1ksim/README
1066	readme updated	markom	8101d 20h	/or1k/branches/stable_0_1_x/or1ksim/README
879	Initial version of OpenRISC Custom Unit Compiler added	markom	8210d 13h	/or1k/branches/stable_0_1_x/or1ksim/README
72	Added 'how to build GNU tools'	lampret	8834d 23h	/or1k/branches/stable_0_1_x/or1ksim/README
54	Regular maintenance.	lampret	8892d 23h	/or1k/branches/stable_0_1_x/or1ksim/README
21	More modifications related to or16.	cmchen	9002d 08h	/or1k/branches/stable_0_1_x/or1ksim/README
18	or16 added, or1k renamed to or32.	lampret	9002d 22h	/or1k/branches/stable_0_1_x/or1ksim/README
12	Added information to the section about how to configure and compile the package.	jrydberg	9063d 14h	/or1k/branches/stable_0_1_x/or1ksim/README
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	9064d 08h	/or1k/branches/stable_0_1_x/or1ksim/README
4	no message	lampret	9114d 12h	/or1k/branches/stable_0_1_x/or1ksim/README
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	cvs	9190d 02h	/or1k/branches/stable_0_1_x/or1ksim/README
2	First import.	cvs	9190d 02h	/or1k/branches/stable_0_1_x/or1ksim/README