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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cache/] [dcache_model.c] - Rev 1771

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1765 root 5767d 14h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7256d 02h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7257d 19h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7270d 23h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7462d 13h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1085 Bug fixed. simons 8069d 15h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8159d 04h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
992 A bug when cache enabled and bus error comes fixed. simons 8160d 19h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8203d 02h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
638 TLBTR CI bit is now working properly. simons 8361d 15h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
631 Real cache access is simulated now. simons 8364d 14h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8385d 23h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
428 cache configuration added markom 8413d 22h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8453d 03h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8538d 22h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8621d 08h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
54 Regular maintenance. lampret 8891d 05h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
26 Clean up. lampret 8998d 09h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
5 Data and instruction cache simulation added. lampret 9062d 15h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c

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