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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cache/] [icache_model.c] - Rev 1777

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1765 root 5719d 16h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7208d 04h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7209d 21h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7223d 01h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7414d 15h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
1085 Bug fixed. simons 8021d 17h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8111d 06h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
992 A bug when cache enabled and bus error comes fixed. simons 8112d 21h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8155d 04h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
638 TLBTR CI bit is now working properly. simons 8313d 18h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
631 Real cache access is simulated now. simons 8316d 16h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8338d 02h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
429 cache configuration added markom 8366d 00h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
428 cache configuration added markom 8366d 00h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8405d 05h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8491d 00h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
110 bug fix. markom 8569d 03h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8573d 10h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
76 regular update lampret 8773d 07h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c
26 Clean up. lampret 8950d 11h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.c

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