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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cache/] [icache_model.h] - Rev 1768

Rev	Log message	Author	Age	Path
1765		root	5769d 20h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
1356	This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'.		7258d 08h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7260d 01h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7464d 19h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
631	Real cache access is simulated now.	simons	8366d 20h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
429	cache configuration added	markom	8416d 04h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8623d 13h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
76	regular update	lampret	8823d 11h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
5	Data and instruction cache simulation added.	lampret	9064d 21h	/or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h