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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cache/] [icache_model.h] - Rev 1771

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1765 root 5767d 15h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7256d 03h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7257d 20h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
1308 Gyorgy Jeney: extensive cleanup phoenix 7462d 14h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
631 Real cache access is simulated now. simons 8364d 15h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
429 cache configuration added markom 8413d 23h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8621d 08h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
76 regular update lampret 8821d 06h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h
5 Data and instruction cache simulation added. lampret 9062d 16h /or1k/branches/stable_0_1_x/or1ksim/cache/icache_model.h

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