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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cpu/] [dlx/] [execute.c] - Rev 1768

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1765 root 5770d 11h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7258d 23h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8162d 01h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
393 messages: exception on many places changed to abort markom 8430d 02h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
123 Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault

Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files		 markom 8598d 20h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
30 Updated SPRs, exceptions. Added 16450 device. lampret 8970d 11h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 9065d 12h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 cvs 9191d 05h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c
2 First import. cvs 9191d 05h /or1k/branches/stable_0_1_x/or1ksim/cpu/dlx/execute.c

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