OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Rev 1767

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5628d 15h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7117d 03h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7118d 20h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7132d 00h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1343 * Fix warnings in insnset.c and execute.c nogj 7132d 00h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
nogj 7132d 00h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1338 l.ff1 instruction added andreje 7147d 22h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1321 some tests rely on exit(0) as a last std output text to pass phoenix 7233d 15h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7235d 15h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7323d 14h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1303 compile fix regarding lf.itof.s, lf.itof.d phoenix 7341d 02h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1244 Added "cm" command to copy data inside memory.
Make or1ksim work on little endian platforms.
Port to Mac OS X.
Some bugfixes.
Allow JTAG write access to read-only memory regions.
hpanther 7490d 23h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
1170 Added support for l.addc instruction. csanchez 7707d 18h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8020d 05h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8064d 03h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
722 floating point registers are obsolete; GPRs should be used instead markom 8190d 00h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
720 single floating point support added markom 8190d 04h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
713 lot of small minor improvements: code documented, cleaned; runs at about same speed when not actually logging, but exe_log is enabled; raw_stats now run only with simple execution - enable RAW_USAGE_STATS macro markom 8192d 04h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
712 eval_operand and set_operand functions are being generated markom 8195d 01h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c
706 insn_decode execution part replaced by generated function decode_execute; use --enable-simple to use runtime decoding markom 8196d 00h /or1k/branches/stable_0_1_x/or1ksim/cpu/or32/insnset.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.