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Rev	Log message	Author	Age	Path
1765		root	5769d 19h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1356	This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'.		7258d 08h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7260d 00h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1308	Gyorgy Jeney: extensive cleanup	phoenix	7464d 19h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1244	Added "cm" command to copy data inside memory. Make or1ksim work on little endian platforms. Port to Mac OS X. Some bugfixes. Allow JTAG write access to read-only memory regions.	hpanther	7632d 04h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1103	sync problem in cuc not yet fixed	markom	8059d 03h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1102	few cuc bug fixes	markom	8059d 03h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1101	cuc now compiles	markom	8059d 06h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1098	small bug in cuc fixed	markom	8059d 07h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1061	ELF sym loading improved	markom	8113d 04h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1059	several cuc bugs fixed; different verilog cuc file naming	markom	8126d 03h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1048	breakpoint can be set on labels	markom	8141d 03h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
1001	fixed load/store state machine verilog generation errors	markom	8161d 05h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
997	PRINTF should be used instead of printf; command redirection repaired	markom	8161d 09h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
996	some minor bugs fixed	markom	8162d 08h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
986	outputs out of function are not registered anymore	markom	8165d 08h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
973	generated cuc top scheduler builds without syntax errors; not tested yet	markom	8168d 04h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
940	profiling and cuc can be made in one run	markom	8176d 03h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
937	added file; cleanup	markom	8176d 10h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c
933	adding fact generation from conditionals; still under development	markom	8178d 07h	/or1k/branches/stable_0_1_x/or1ksim/cuc/verilog.c

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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cuc/] [verilog.c] - Rev 1768

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