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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [cache.c] - Rev 1775

Rev	Log message	Author	Age	Path
1765		root	5755d 04h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
1356	This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'.		7243d 17h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
631	Real cache access is simulated now.	simons	8352d 05h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
621	Cache test works on hardware.	simons	8353d 17h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
575	Not needed to be compiled with -O2 optimization any more.	simons	8366d 15h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
574	fixed some tests to work	markom	8366d 17h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
534	Changed to work with new simulator.	simons	8374d 14h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
484	Changed to support execution from various addresses.	simons	8393d 08h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
424	memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory	markom	8401d 16h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
349	Some bugs regarding cache simulation fixed.	simons	8426d 07h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
322	IC test repaired.C	simons	8432d 09h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c
224	added various tests	markom	8449d 15h	/or1k/branches/stable_0_1_x/or1ksim/testbench/cache.c