OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [mmu.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5572d 11h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7061d 00h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 7951d 22h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7964d 01h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
970 Testbench is now running on ORP architecture platform. simons 7971d 12h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 7973d 14h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
639 MMU cache inhibit bit test added. simons 8166d 13h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8179d 11h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
509 unused var warning corrected markom 8195d 20h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
480 RTL_SIM define added for shorter simulation runtime. simons 8210d 19h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
466 EEAR is used for determing ITLB miss and IPF page address. simons 8211d 12h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
457 Page size set to 8192. simons 8215d 15h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
448 Permission test added. simons 8217d 01h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
417 ITLB test tested on simulator. simons 8221d 10h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
415 DTLB test tested on simulator. simons 8222d 11h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
413 some section changes markom 8222d 20h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
412 *** empty log message *** simons 8222d 21h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c
410 MMU test added. simons 8223d 18h /or1k/branches/stable_0_1_x/or1ksim/testbench/mmu.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.